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87
Voted
ISSS
2002
IEEE
176views Hardware» more  ISSS 2002»
15 years 5 months ago
Controller Estimation for FPGA Target Architectures during High-Level Synthesis
In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence,...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
107
Voted
ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
15 years 5 months ago
Validation in a Component-Based Design Flow for Multicore SoCs
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable...
Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima,...
99
Voted
ISSS
2002
IEEE
126views Hardware» more  ISSS 2002»
15 years 5 months ago
Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design
In this paper, we present a new methodology for application specific multiprocessor system-on-chip design. This approach facilitates the integration of existing components with th...
Ahmed Amine Jerraya, Damien Lyonnard, Samy Meftali...
76
Voted
ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
15 years 5 months ago
An Adaptive Low-Power Transmission Scheme for On-Chip Networks
Paolo Ienne, Patrick Thiran, Giovanni De Micheli, ...
67
Voted
ISSS
2002
IEEE
106views Hardware» more  ISSS 2002»
15 years 5 months ago
Modeling Assembly Instruction Timing in Superscalar Architectures
This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provi...
William Fornaciari, Vito Trianni, Carlo Brandolese...
121
Voted
ISSS
2002
IEEE
124views Hardware» more  ISSS 2002»
15 years 5 months ago
A New Performance Evaluation Approach for System Level Design Space Exploration
Application specific systems have potential for customization of design with a view to achieve a better costperformance-power trade-off. Such customization requires extensive de...
M. Balakrishnan, Anshul Kumar, C. P. Joshi
ISSS
2002
IEEE
136views Hardware» more  ISSS 2002»
15 years 5 months ago
Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors
This paper presents a new technique for global energy optimization through coordinated functional partitioning and speed selection for embedded processors interconnected by a high...
Nader Bagherzadeh, Pai H. Chou, Jinfeng Liu
98
Voted
ISSS
2002
IEEE
120views Hardware» more  ISSS 2002»
15 years 5 months ago
Virtual Synchronization for Fast Distributed Cosimulation of Dataflow Task Graphs
Fast distributed cosimulation is a challenging problem for the embedded system design. The main theme of this paper is to increase simulation speed by reducing the frequency of in...
Soonhoi Ha, Sungchan Kim, Chan-Eun Rhee, Hyunguk J...
82
Voted
ISSS
2002
IEEE
133views Hardware» more  ISSS 2002»
15 years 5 months ago
Efficient Simulation of Synthesis-Oriented System Level Designs
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu
83
Voted
ISSS
2002
IEEE
95views Hardware» more  ISSS 2002»
15 years 5 months ago
Datapath Merging and Interconnection Sharing for Reconfigurable Architectures
Guido Araujo, Sharad Malik, Zhining Huang, Nahri M...