148
Voted
ICPP
2009
IEEE
15 years 14 days ago
2009
IEEE
The emergence of multicore processors raises the need to efficiently transfer large amounts of data between local processes. MPICH2 is a highly portable MPI implementation whose l...
130
Voted
HIPC
2009
Springer
15 years 15 days ago
2009
Springer
Modern processors dedicate more than half their chip area to large L2 and L3 caches and these caches contribute significantly to the total processor power. A large cache is typica...
124
Voted
HIPC
2009
Springer
15 years 15 days ago
2009
Springer
In many-core architectures, memory blocks are commonly assigned to the banks of a NUCA cache by following a physical mapping. This mapping assigns blocks to cache banks in a round-...
141
Voted
ECRTS
2009
IEEE
15 years 16 days ago
2009
IEEE
While hardware caches are generally effective at improving application performance, they greatly complicate performance prediction. Slight changes in memory layout or data access p...
117
Voted
ANCS
2009
ACM
15 years 17 days ago
2009
ACM
This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacit...
119
Voted
MICRO
2010
IEEE
15 years 19 days ago
2010
IEEE
Energy efficiency is a primary concern for microprocessor designers. A very effective approach to improving the energy efficiency of a chip is to lower its supply voltage to very ...
119
Voted
MICRO
2010
IEEE
15 years 19 days ago
2010
IEEE
The ever-increasing importance of main memory latency and bandwidth is pushing CMPs towards caches with higher capacity and associativity. Associativity is typically improved by in...
119
Voted
ISW
2010
Springer
15 years 20 days ago
2010
Springer
Recently, a new scheme to protect clients against DNS cache poisoning attacks was introduced. The scheme is referred to as DepenDNS and is intended to protect clients against such ...
123
Voted
IPPS
2010
IEEE
15 years 20 days ago
2010
IEEE
Multi-core organizations increasingly support multiple threads per core. Threads on a core usually share a single first-level data cache, so thread schedulers must try to minimize ...
129
Voted
IPPS
2010
IEEE
15 years 20 days ago
2010
IEEE
Abstract-- Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache par...