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133
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ICCD
2007
IEEE
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ICCD 2007
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Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits
16 years 1 hour ago
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www.ecse.rpi.edu
Hybrid nanoelectronics are emerging as one viable option to sustain the Moore’s Law after the CMOS scaling limit is reached. One main design challenge in hybrid nanoelectronics ...
Shu Li, Tong Zhang
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