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121
Voted
CODES
1999
IEEE
15 years 6 months ago
A unified formal model of ISA and FSMD
In this paper, we develop a formal framework to widen the scope of retargetable compilation. The goal is achieved by the unification of architectural models for both the processor...
Jianwen Zhu, Daniel Gajski
CODES
1999
IEEE
15 years 6 months ago
A probabilistic performance metric for real-time system design
Tao Zhou, Xiaobo Sharon Hu, Edwin Hsing-Mean Sha
136
Voted
CODES
1999
IEEE
15 years 6 months ago
Optimizing geographically distributed timed cosimulation by hierarchically grouped messages
raction levels of communication models to allow designers to trade off between performance and accuracy. Contrary to [2][3], we present an optimization method which preserves the a...
Sungjoo Yoo, Kiyoung Choi
CODES
1999
IEEE
15 years 6 months ago
Using codesign techniques to support analog functionality
With the growth of System on a Chip (SoC), the functionality of analog components must also be considered in the design process. This paper describes some of the design implementa...
Francis G. Wolff, Michael J. Knieser, Daniel J. We...
144
Voted
CODES
1999
IEEE
15 years 6 months ago
An MPEG-2 decoder case study as a driver for a system level design methodology
We present a case study on the design of a heterogeneous architecture for MPEG-2 video decoding. The primary objective of the case study is the validation of the SPADE methodology...
Pieter van der Wolf, Paul Lieverse, Mudit Goel, Da...
121
Voted
CODES
1999
IEEE
15 years 6 months ago
System synthesis utilizing a layered functional model
We propose a system synthesis method which bridges the gap between a highly abstract functional model and an efficient hardware or software implementation. The functional model is...
Ingo Sander, Axel Jantsch
88
Voted
CODES
1999
IEEE
15 years 6 months ago
Timing-driven HW/SW codesign based on task structuring and process timing simulation
Dinesh Ramanathan, Ali Dasdan, Rajesh K. Gupta
93
Voted
CODES
1999
IEEE
15 years 6 months ago
Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor
Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsa...
CODES
1999
IEEE
15 years 6 months ago
Scheduling with optimized communication for time-triggered embedded systems
We present an approach to process scheduling for synthesis of safety-critical distributed embedded systems. Our system model captures both the flow of data and that of control. Th...
Paul Pop, Petru Eles, Zebo Peng