Sciweavers

DAC
2001
ACM
16 years 1 months ago
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
Kaustav Banerjee, Amit Mehrotra
DAC
2001
ACM
16 years 1 months ago
Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs
Non-uniform temperature profiles along global interconnect lines in high-performance ICs can significantly impact the performance of these lines. This paper presents a detailed an...
Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, L...
DAC
2001
ACM
16 years 1 months ago
A Practical Methodology for Early Buffer and Wire Resource Allocation
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar,...
DAC
2000
ACM
16 years 1 months ago
Hierarchical analysis of power distribution networks
Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, T...
95
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DAC
2000
ACM
16 years 1 months ago
System chip test: how will it impact your design?
A major challenge in realizing core-based system chips is the adoption and design-in of adequate test and diagnosis strategies. This tutorial paper discusses the specific challeng...
Yervant Zorian, Erik Jan Marinissen
DAC
2000
ACM
16 years 1 months ago
The use of carry-save representation in joint module selection and retiming
Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In ...
Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.
DAC
2000
ACM
16 years 1 months ago
The design and use of simplepower: a cycle-accurate energy estimation tool
In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for evaluating the e ect of high-level algorithmic, architectural, and compilation tradeo...
Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir...
DAC
2000
ACM
16 years 1 months ago
MINFLOTRANSIT: min-cost flow based transistor sizing tool
This paper presents MINFLOTRANSIT, a new transistor sizing tool for fast sizing of combinational circuits with minimal cost. MINFLOTRANSIT is an iterative relaxation based tool th...
Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K...