Sciweavers

DFT
2003
IEEE
108views VLSI» more  DFT 2003»
14 years 4 months ago
Control Constrained Resource Partitioning for Complex SoCs
Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
DFT
2003
IEEE
81views VLSI» more  DFT 2003»
14 years 4 months ago
A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment
Fengming Zhang, Young-Jun Lee, T. Kane, Luca Schia...
DFT
2003
IEEE
154views VLSI» more  DFT 2003»
14 years 4 months ago
Fault Recovery Based on Checkpointing for Hard Real-Time Embedded Systems
Safety-critical embedded systems often operate in harsh environmental conditions that necessitate fault-tolerant computing techniques. Many safety-critical systems also execute re...
Ying Zhang, Krishnendu Chakrabarty
DFT
2003
IEEE
99views VLSI» more  DFT 2003»
14 years 4 months ago
Quadruple Time Redundancy Adders
Whitney J. Townsend, Jacob A. Abraham, Earl E. Swa...
DFT
2003
IEEE
142views VLSI» more  DFT 2003»
14 years 4 months ago
Exploiting Instruction Redundancy for Transient Fault Tolerance
This paper presents an approach for integrating fault-tolerance techniques into microprocessors by utilizing instruction redundancy as well as time redundancy. Smaller and smaller...
Toshinori Sato
DFT
2003
IEEE
86views VLSI» more  DFT 2003»
14 years 4 months ago
CROWNE: Current Ratio Outliers with Neighbor Estimator
Increased leakage and process variations make distinction between fault-free and faulty chips by IDDQ test difficult. Earlier the concept of Current Ratios (CR) was proposed to sc...
Sagar S. Sabade, D. M. H. Walker
DFT
2003
IEEE
246views VLSI» more  DFT 2003»
14 years 4 months ago
Low Cost Convolutional Code Based Concurrent Error Detection in FSMs
We discuss the use of convolutional codes to perform concurrent error detection (CED) in finite state machines (FSMs). We examine a previously proposed methodology, we identify i...
Konstantinos Rokas, Yiorgos Makris, Dimitris Gizop...
DFT
2003
IEEE
114views VLSI» more  DFT 2003»
14 years 4 months ago
CodSim -- A Combined Delay Fault Simulator
Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this ...
Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, We...
DFT
2003
IEEE
99views VLSI» more  DFT 2003»
14 years 4 months ago
Dependability Analysis of CAN Networks: An Emulation-Based Approach
1 Today many safety-critical applications are based on distributed systems where several computing nodes exchange information via suitable network interconnections. An example of t...
J. Pérez, Matteo Sonza Reorda, Massimo Viol...
DFT
2003
IEEE
79views VLSI» more  DFT 2003»
14 years 4 months ago
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits
A new methodology for designing logic circuits with partial error masking is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic cir...
Kartik Mohanram, Nur A. Touba