Sciweavers

GLVLSI
2008
IEEE
140views VLSI» more  GLVLSI 2008»
15 years 3 months ago
A table-based method for single-pass cache optimization
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank V...
83
Voted
GLVLSI
2008
IEEE
147views VLSI» more  GLVLSI 2008»
15 years 3 months ago
Statistical timing analysis of flip-flops considering codependent setup and hold times
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
Safar Hatami, Hamed Abrishami, Massoud Pedram
GLVLSI
2008
IEEE
121views VLSI» more  GLVLSI 2008»
15 years 3 months ago
FEKIS: a fast architecture-level thermal analyzer for online thermal regulation
Pu Liu, Sheldon X.-D. Tan, Wei Wu, Murli Tirumala
GLVLSI
2008
IEEE
157views VLSI» more  GLVLSI 2008»
15 years 3 months ago
Coverage-driven automatic test generation for uml activity diagrams
Due to the increasing complexity of today’s embedded systems, the analysis and validation of such systems is becoming a major challenge. UML is gradually adopted in the embedded...
Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita
GLVLSI
2008
IEEE
112views VLSI» more  GLVLSI 2008»
15 years 3 months ago
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
Maziar Goudarzi, Tohru Ishihara
GLVLSI
2008
IEEE
129views VLSI» more  GLVLSI 2008»
15 years 3 months ago
Variational capacitance modeling using orthogonal polynomial method
In this paper, we propose a novel statistical capacitance extraction method for interconnects considering process variations. The new method, called statCap, is based on the spect...
Jian Cui, Gengsheng Chen, Ruijing Shen, Sheldon X....
GLVLSI
2008
IEEE
117views VLSI» more  GLVLSI 2008»
15 years 3 months ago
Delay driven AIG restructuring using slack budget management
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
GLVLSI
2008
IEEE
120views VLSI» more  GLVLSI 2008»
15 years 3 months ago
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Novel nano-scale devices have shown promising potential to overcome physical barriers faced by complementary metaloxide semiconductor (CMOS) technology in future circuit design. H...
Yexin Zheng, Michael S. Hsiao, Chao Huang
GLVLSI
2008
IEEE
204views VLSI» more  GLVLSI 2008»
15 years 3 months ago
NBTI resilient circuits using adaptive body biasing
Reliability has become a practical concern in today’s VLSI design with advanced technologies. In-situ sensors have been proposed for reliability monitoring to provide advance wa...
Zhenyu Qi, Mircea R. Stan