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139
Voted
ICCAD
2005
IEEE
134views Hardware» more  ICCAD 2005»
15 years 10 months ago
Fast thermal simulation for architecture level dynamic thermal management
As power density increases exponentially, runtime regulation of operating temperature by dynamic thermal managements becomes necessary. This paper proposes a novel approach to the...
Pu Liu, Zhenyu Qi, Hang Li, Lingling Jin, Wei Wu, ...
118
Voted
ICCAD
2005
IEEE
140views Hardware» more  ICCAD 2005»
15 years 10 months ago
Embedded tutorial: formal equivalence checking between system-level models and RTL
Alfred Koelbl, Yuan Lu, Anmol Mathur
124
Voted
ICCAD
2005
IEEE
199views Hardware» more  ICCAD 2005»
15 years 10 months ago
FinFETs for nanoscale CMOS digital integrated circuits
Suppression of leakage current and reduction in device-todevice variability will be key challenges for sub-45nm CMOS technologies. Non-classical transistor structures such as the ...
Tsu-Jae King
ICCAD
2005
IEEE
73views Hardware» more  ICCAD 2005»
15 years 10 months ago
The feasibility of on-chip interconnection using antennas
K. O. Kenneth, Kihong Kim, Brian A. Floyd, Jesal L...
98
Voted
ICCAD
2005
IEEE
83views Hardware» more  ICCAD 2005»
15 years 10 months ago
System software techniques for low-power operation in wireless sensor networks
Prabal Dutta, David E. Culler
ICCAD
2005
IEEE
71views Hardware» more  ICCAD 2005»
15 years 10 months ago
Simulation-based bug trace minimization with BMC-based refinement
Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
136
Voted
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
15 years 10 months ago
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...
Ankur Agiwal, Montek Singh
148
Voted
FPT
2005
IEEE
170views Hardware» more  FPT 2005»
15 years 10 months ago
High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences
This paper describes a class of FPGA-specific uniform random number generators with a 2k −1 length period, which can provide k random bits per-cycle for the cost of k Lookup Ta...
David B. Thomas, Wayne Luk
FPT
2005
IEEE
163views Hardware» more  FPT 2005»
15 years 10 months ago
Designing an FPGA SoC Using a Standardized IP Block Interface
Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Element...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...