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    2011
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    Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
    14 years 4 months ago
    Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
    Download  cccp.eecs.umich.edu
    —Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
    Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
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