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    CODES
    2011
    IEEE
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    Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
    14 years 1 days ago
    Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
    Download  cseart.ucsd.edu
    Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
    Garo Bournoutian, Alex Orailoglu
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