Sciweavers

78
Voted
ET
2002
64views more  ET 2002»
14 years 10 months ago
Structural Fault Based Specification Reduction for Testing Analog Circuits
Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is prop...
Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen