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111
Voted
DFT
2008
IEEE
117
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VLSI
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DFT 2008
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Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS
15 years 9 months ago
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infocenter.arm.com
With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based ...
Vikas Chandra, Robert C. Aitken
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