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ICST
2010
IEEE
13 years 3 months ago
Fault Detection Likelihood of Test Sequence Length
— Testing of graphical user interfaces is important due to its potential to reveal faults in operation and performance of the system under consideration. Most existing test appro...
Fevzi Belli, Michael Linschulte, Christof J. Budni...
ET
2002
84views more  ET 2002»
13 years 4 months ago
Hardware Generation of Random Single Input Change Test Sequences
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
René David, Patrick Girard, Christian Landr...
DT
2000
162views more  DT 2000»
13 years 4 months ago
RT-Level ITC'99 Benchmarks and First ATPG Results
Effective high-level ATPG tools are increasingly needed, as an essential element in the quest for reducing as much as possible the designer work on gate-level descriptions. We pro...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
PTS
1993
106views Hardware» more  PTS 1993»
13 years 5 months ago
Generating Synchronizable Test Sequences Based on Finite State Machine with Distributed Ports
In the area of testing communication systems, the interfaces between systems to be tested and their testers have great impact on test generation and fault detectability. Several t...
Gang Luo, Rachida Dssouli, Gregor von Bochmann, Pa...
EURODAC
1995
IEEE
164views VHDL» more  EURODAC 1995»
13 years 8 months ago
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
Srimat T. Chakradhar, Anand Raghunathan
TACAS
1997
Springer
132views Algorithms» more  TACAS 1997»
13 years 8 months ago
Test Generation for Intelligent Networks Using Model Checking
We study the use of model checking techniques for the generation of test sequences. Given a formal model of the system to be tested, one can formulate test purposes. A model checke...
André Engels, Loe M. G. Feijs, Sjouke Mauw
VTS
1997
IEEE
96views Hardware» more  VTS 1997»
13 years 8 months ago
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors
Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a sm...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
ITC
1997
IEEE
73views Hardware» more  ITC 1997»
13 years 8 months ago
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
VTS
2000
IEEE
113views Hardware» more  VTS 2000»
13 years 8 months ago
Hidden Markov and Independence Models with Patterns for Sequential BIST
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
Laurent Bréhélin, Olivier Gascuel, G...
DATE
2000
IEEE
113views Hardware» more  DATE 2000»
13 years 9 months ago
Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficien...
Irith Pomeranz, Sudhakar M. Reddy