Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

9

ISQED
2003
IEEE

favoriteEmaildiscussreport

78views Hardware» more ISQED 2003»

An Embedded IDDQ Testing Architecture and Technique

13 years 9 months ago

An Embedded IDDQ Testing Architecture and Technique

Download www.cecs.uci.edu

In this paper an embedded IDDQ testing architecture is presented that targets to overcome the excessive hardware overhead requirements in built-in current sensing based testing applications. Moreover, a technique that utilises the IEEE 1149.1 boundary scan standard to control the proposed architecture is provided. The proposed solution is characterised by low silicon area requirements and permits the application of IDDQ testing also in case that the chip is mounted on a printed circuit board.

Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni

Real-time Traffic

Hardware | Hardware Overhead Requirements | IDDQ Testing Architecture | ISQED 2003 | Sensing Based Testing |

claim paper

Related Content

» DivideandConquer IDDQ Testing for CoreBased System Chips

» Immediate Neighbor Difference IDDQ Test INDIT for Outlier Identification

» Characterization and Estimation of Circuit Reliability Degradation under NBTI using OnLine...

» IC Test Using the Energy Consumption Ratio

» Characterizing withindie variation from multiple supply port IDDQ measurements

» A Design and Test Technique for Embedded Software

» Designs for Reducing Test Time of Distributed Small Embedded SRAMs

» The Logical Execution Time Paradigm

» A Fault Modeling Technique to Test Memory BIST Algorithms

Post Info
More Details (n/a)

Added	04 Jul 2010
Updated	04 Jul 2010
Type	Conference
Year	2003
Where	ISQED
Authors	Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni

Comments (0)