48 search results - page 1 / 10 » An Embedded IDDQ Testing Architecture and Technique |
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
In this paper an embedded IDDQ testing architecture is presented that targets to overcome the excessive hardware overhead requirements in built-in current sensing based testing ap...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
VLSID
2003
IEEE
14 years 5 months ago
2003
IEEE
Increasing values and spread in leakage current makes it impossible to distinguish between faulty and fault-free chips using single threshold method. Neighboring chips on a wafer ...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characte...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
Dynamic-current based test techniques can potentially address the drawbacks of traditional and Iddq test methodologies. The quality of dynamic current based test is degraded by pr...