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9

ITC
2003
IEEE

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Fault Injection for Verifying Testability at the VHDL Level

13 years 10 months ago

Fault Injection for Verifying Testability at the VHDL Level

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This paper presents a technique to improve verification at the VHDL level of digital circuits by means of a specially designed fault injection block. The injection technique allows incorporation of both transient and permanent faults to varying levels of VHDL hierarchy, and helps in verifying the performance of a testable system.

S. R. Seward, Parag K. Lala

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Added	04 Jul 2010
Updated	04 Jul 2010
Type	Conference
Year	2003
Where	ITC
Authors	S. R. Seward, Parag K. Lala

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