10 search results - page 1 / 2 » Fault Injection for Verifying Testability at the VHDL Level |
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper presents a technique to improve verification at the VHDL level of digital circuits by means of a specially designed fault injection block. The injection technique allow...
GLVLSI
1998
IEEE
13 years 9 months ago
1998
IEEE
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
DSD
2009
IEEE
13 years 9 months ago
2009
IEEE
Todays NoCs are reaching a level where it is getting very hard to ensure 100% of functionality. Consequently, fault tolerance has become an important aspect in todays design techn...
EVOW
2001
Springer
13 years 9 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...