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PTS
2010
132views Hardware» more  PTS 2010»
11 years 3 months ago
Increasing Functional Coverage by Inductive Testing: A Case Study
This paper addresses the challenge of generating test sets that achieve functional coverage, in the absence of a complete specification. The inductive testing technique works by p...
Neil Walkinshaw, Kirill Bogdanov, John Derrick, Ja...
TCAD
2008
114views more  TCAD 2008»
11 years 5 months ago
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
Zhanglei Wang, Krishnendu Chakrabarty
NIPS
2004
11 years 6 months ago
Result Analysis of the NIPS 2003 Feature Selection Challenge
The NIPS 2003 workshops included a feature selection competition organized by the authors. We provided participants with five datasets from different application domains and calle...
Isabelle Guyon, Steve R. Gunn, Asa Ben-Hur, Gideon...
SNPD
2008
11 years 6 months ago
A Comparative Evaluation of Tests Generated from Different UML Diagrams
This paper presents a single project experiment on the fault revealing capabilities of model-based test sets. The tests are generated from UML statecharts and UML sequence diagram...
Supaporn Kansomkeat, Jeff Offutt, Aynur Abdurazik,...
FORTEST
2008
11 years 7 months ago
Testing Data Types Implementations from Algebraic Specifications
Algebraic specifications of data types provide a natural basis for testing data types implementations. In this framework, the conformance relation is based on the satisfaction of a...
Marie-Claude Gaudel, Pascale Le Gall
DELTA
2008
IEEE
11 years 7 months ago
Test Set Stripping Limiting the Maximum Number of Specified Bits
This paper presents a technique that limits the maximum number of specified bits of any pattern in a given test set. The outlined method uses algorithms similar to ATPG, but explo...
Michael A. Kochte, Christian G. Zoellin, Michael E...
ATS
2005
IEEE
164views Hardware» more  ATS 2005»
11 years 7 months ago
A Family of Logical Fault Models for Reversible Circuits
Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional ...
Ilia Polian, Thomas Fiehn, Bernd Becker, John P. H...
ICCAD
1995
IEEE
170views Hardware» more  ICCAD 1995»
11 years 9 months ago
Acceleration techniques for dynamic vector compaction
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
Anand Raghunathan, Srimat T. Chakradhar
ICECCS
2000
IEEE
106views Hardware» more  ICECCS 2000»
11 years 9 months ago
Evaluation of Three Specification-Based Testing Criteria
This paper compares three specification-based testing criteria using Mathur and Wong's PROBSUBSUMES measure. The three criteria are specification-mutation coverage, full pred...
Aynur Abdurazik, Paul Ammann, Wei Ding 0003, A. Je...
GECCO
2006
Springer
253views Optimization» more  GECCO 2006»
11 years 9 months ago
A novel approach to optimize clone refactoring activity
Achieving a high quality and cost-effective tests is a major concern for software buyers and sellers. Using tools and integrating techniques to carry out low cost testing are chal...
Salah Bouktif, Giuliano Antoniol, Ettore Merlo, Ma...
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