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8

DAC
1997
ACM

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75views Computer Architecture» more DAC 1997»

Efficient Testing of Clock Regenerator Circuits in Scan Designs

13 years 9 months ago

Efficient Testing of Clock Regenerator Circuits in Scan Designs

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Rajesh Raina, Robert Bailey, Charles Njinda, Rober

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Computer Architecture | DAC 1997 |

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Added	06 Aug 2010
Updated	06 Aug 2010
Type	Conference
Year	1997
Where	DAC
Authors	Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh

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