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TVLSI
2010
8 years 10 months ago
On the Power Management of Simultaneous Multithreading Processors
SMT processors are widely used in high performance computing tasks. However, with the improved performance of the SMT architecture, the utilization of their functional units is sig...
Ahmed Youssef, Mohamed Zahran, Mohab Anis, Mohamed...
TCAD
2010
110views more  TCAD 2010»
8 years 10 months ago
Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power
Abstract--In sub-100 nm CMOS processes, delay and leakage power reduction continue to be among the most critical design concerns. We propose to exploit the recent availability of f...
Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Ha...
TVLSI
2008
153views more  TVLSI 2008»
9 years 3 months ago
Characterization of a Novel Nine-Transistor SRAM Cell
Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors...
Zhiyu Liu, Volkan Kursun
TCAD
2008
115views more  TCAD 2008»
9 years 3 months ago
Statistical Thermal Profile Considering Process Variations: Analysis and Applications
The nonuniform substrate thermal profile and process variations are two major concerns in the present-day ultradeep submicrometer designs. To correctly predict performance/ leakage...
Javid Jaffari, Mohab Anis
TC
2008
9 years 3 months ago
On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance
This paper describes a new on-demand wake-up prediction policy for reducing leakage power. The key insight is that branch prediction can be used to selectively wake up only the nee...
Sung Woo Chung, Kevin Skadron
CORR
2010
Springer
90views Education» more  CORR 2010»
9 years 3 months ago
Level Shifter Design for Low Power Applications
With scaling of Vt sub-threshold leakage power is increasing and expected to become significant part of total power consumption.In present work three new configurations of level s...
Manoj Kumar, Sandeep K. Arya, Sujata Pandey
DAC
2008
ACM
9 years 5 months ago
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
Min Ni, Seda Ogrenci Memik
CF
2005
ACM
9 years 5 months ago
Drowsy region-based caches: minimizing both dynamic and static power dissipation
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
CF
2005
ACM
9 years 5 months ago
Controlling leakage power with the replacement policy in slumberous caches
As technology scales down at an exponential rate, leakage power is fast becoming the dominant component of the total power budget. A large share of the total leakage power is diss...
Nasir Mohyuddin, Rashed Bhatti, Michel Dubois
ASPDAC
2005
ACM
149views Hardware» more  ASPDAC 2005»
9 years 5 months ago
Leakage control in FPGA routing fabric
Abstract— As FPGA designs in 65nm are being explored, reducing leakage power becomes an important design issue. A significant portion of the FPGA leakage is expended in the unus...
Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykr...
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