Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA

Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. However, this approach results in inefficient memory utilization. Due to available on-chip memory and pin limitations of FPGAs, stateof-the-art designs on FPGAs cannot support large routing tables arising in backbone routers. Therefore, ternary content addressable memory (TCAM) is widely used. We propose a novel SRAM-based linear pipeline architecture, named DuPI. Using a single Virtex-4, DuPI can support a routing table of up to 228K prefixes, which is 3

• Type: Conference
• Year: 2008
• Where: FPL
• Authors: Hoang Le, Weirong Jiang, Viktor K. Prasanna
• Keywords: Available On-chip Memory, FPL 2008, Hardware, Inefficient Memory Utilization, Routing Tables