Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs

Abstract This paper presents an embedded system design toolchain for automatic generation of parallel code runnable on symmetric multiprocessor systems from an initial sequential specification written using the C language. We show how the initial C specification is translated in a modified system dependence graph with feedback edges (FSDG) composing the intermediate representation which is manipulated by the algorithm. Then we describe how this graph is partitioned and optimized: at the end of the process each partition (cluster of nodes) represents a different task. The parallel C code produced is such that the tasks can be dynamically scheduled on the target architecture; this is obtained thanks to the introduction of start conditions for each task. We present the experimental results obtained by applying our flow on the sequential code of the ADPCM and JPEG algorithms and running the parallel specification produced by the toolchain on the target platform: with respect to the se...

• Type: Conference
• Year: 2007
• Where: IESS
• Authors: Fabrizio Ferrandi, Luca Fossati, Marco Lattuada, Gianluca Palermo, Donatella Sciuto, Antonino Tumeo
• Keywords: Embedded Systems, IESS 2007, Initial Sequential Specification, Sequential Specification, Symmetric Multiprocessor Systems