1381 search results - page 1 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Critical issues in designing a high speed, low power static RAM in deep submicron technologies are described along with the design techniques used to overcome them. With appropria...
ISQED
2006
IEEE
13 years 11 months ago
2006
IEEE
It is well known that SRAM constitutes a large portion of modern integrated circuits, with 80% or more of the total transistors being dedicated to SRAM in a typical processor or S...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
TVLSI
2008
13 years 4 months ago
2008
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...