This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
— In this paper, we have proposed a thermal aware routing based parameterization to generate a clock model that takes the stochastic temperature variation into consideration. The...
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...