Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

10

GLVLSI
1996
IEEE

favoriteEmaildiscussreport

128views VLSI» more GLVLSI 1996»

Delay Hazards in Complex Gate Based Speed Independent VLSI Circuits

13 years 8 months ago

Delay Hazards in Complex Gate Based Speed Independent VLSI Circuits

Download www.cecs.uci.edu

Nozar Tabrizi, Michael J. Liebelt, Kamran Eshraghi

Real-time Traffic

GLVLSI 1996 | VLSI |

claim paper

Related Content

» Avoiding Hazards for SpeedIndependent Logic Design

» Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits

» Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Const...

» Novel architectures for efficient m n parallel counters

» The Evolutionary Design and Synthesis of NonLinear Digital VLSI Systems

» Accelerating Retiming Under the CoupledEdge Timing Model

» Process variation dimension reduction based on SVD

» Block alignment in 3D floorplan using layered TCG

» Buffered Routing Tree Construction under Buffer Placement Blockages

Post Info
More Details (n/a)

Added	07 Aug 2010
Updated	07 Aug 2010
Type	Conference
Year	1996
Where	GLVLSI
Authors	Nozar Tabrizi, Michael J. Liebelt, Kamran Eshraghian

Comments (0)