15 search results - page 1 / 3 » Delay Hazards in Complex Gate Based Speed Independent VLSI C... |
GLVLSI
1996
IEEE
13 years 9 months ago
1996
IEEE
WCE
2007
13 years 6 months ago
2007
- In the speed-independent logic, the hazards caused by input inverters are identified. The known methods of the elimination of such hazards are based on avoiding input inverters. ...
VLSI
2005
Springer
13 years 10 months ago
2005
Springer
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
DSD
2010
IEEE
13 years 2 months ago
2010
IEEE
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementati...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...