Delay Uncertainty Reduction by Interconnect and Gate Splitting

Traditional timing variation reduction techniques are only able to decrease the gate delay variation by incurring a delay overhead. In this work, we propose novel and effective splitting based variation reduction techniques for both interconnect and gate. We developed a new tool called TURGIS: Timing Uncertainty Reduction by Gate-Interconnect Splitting which reduces the timing variations of a circuit and presents little delay overhead at the primary output. It is shown that using splitting on interconnect can reduce the Chemical-Mechanical Polishing (CMP) induced dishing effect and can result in decrease at an average of 5% in mean interconnect delay in addition to its variation. Improvements of up to 30% are achieved on timing variation for gates of various size while reduction of 55% can be observed in interconnect delay variation.

• Type: Conference
• Year: 2007
• Where: ASPDAC
• Authors: Vineet Agarwal, Jin Sun, Alexander V. Mitev, Janet Meiling Wang
• Keywords: ASPDAC 2007, Delay Variation, Hardware, Timing Variation, Variation Reduction Techniques