20 search results - page 1 / 4 » Delay Uncertainty Reduction by Interconnect and Gate Splitti... |
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
Traditional timing variation reduction techniques are only able to decrease the gate delay variation by incurring a delay overhead. In this work, we propose novel and effective sp...
DAC
1995
ACM
13 years 8 months ago
1995
ACM
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effectiv...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage r...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...