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11

ITC
1998
IEEE

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Detecting resistive shorts for CMOS domino circuits

13 years 9 months ago

Detecting resistive shorts for CMOS domino circuits

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We investigate defects in CMOS domino gates and derive the test conditions for them. Very-Low-Voltage Testing can improve the defect coverage, which we define as the maximum detectable resistance, of intra-gate and inter-gate resistive shorts. We also propose a new keeper design for CMOS domino circuits. The new keeper design has low performance impact and is best useful for small CMOS domino gates. Keepers can eliminate the floating nodes in CMOS domino logic gates.

Jonathan T.-Y. Chang, Edward J. McCluskey

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Added	05 Aug 2010
Updated	05 Aug 2010
Type	Conference
Year	1998
Where	ITC
Authors	Jonathan T.-Y. Chang, Edward J. McCluskey

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