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GLVLSI
2007
IEEE

The effect of temperature on cache size tuning for low energy embedded systems

11 years 14 days ago
The effect of temperature on cache size tuning for low energy embedded systems
Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for about 40% or more of the total energy consumed in these systems. In older technology nodes, active power was the primary contributor to total power dissipation of a CMOS design. However, with the scaling of feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Temperature is a factor which exponentially increases the leakage current. In this paper, we show the effects of temperature on the selection of optimal cache size for low energy embedded systems. Our results show that for a given application, the optimal cache size selection is affected by the temperature. Our experiments have been done for 100nm technology. Our study reveals that the cache size selection for different temperatures depends on the rate at which cache miss increases when reducing the cache size. When the miss rate increases sharply the optim...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki
Added 02 Jun 2010
Updated 02 Jun 2010
Type Conference
Year 2007
Where GLVLSI
Authors Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami
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