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ISQED
2003
IEEE

An Embedded IDDQ Testing Architecture and Technique

10 years 3 months ago
An Embedded IDDQ Testing Architecture and Technique
In this paper an embedded IDDQ testing architecture is presented that targets to overcome the excessive hardware overhead requirements in built-in current sensing based testing applications. Moreover, a technique that utilises the IEEE 1149.1 boundary scan standard to control the proposed architecture is provided. The proposed solution is characterised by low silicon area requirements and permits the application of IDDQ testing also in case that the chip is mounted on a printed circuit board.
Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ISQED
Authors Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni
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