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2010
Springer
8 years 6 months ago
A new multi-objective optimization formulation for rail-car fleet sizing problems
Abstract With potential application to a variety of industries, fleet sizing problems present a prevalent and significant challenge for engineers and managers. This is especially t...
Hamid Reza Sayarshad, Timothy Marler
JCO
2011
115views more  JCO 2011»
8 years 7 months ago
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
Chen Liao, Shiyan Hu
TCAD
1998
107views more  TCAD 1998»
8 years 11 months ago
Optimizing dominant time constant in RC circuits
— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
Lieven Vandenberghe, Stephen P. Boyd, Abbas A. El ...
TCAD
2008
172views more  TCAD 2008»
8 years 12 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
SIGMETRICS
2008
ACM
9 years 3 hour ago
An SLA perspective on the router buffer sizing problem
In this paper, we discuss recent work on buffer sizing in the context of an ISP's need to offer and guarantee competitive Service Level Agreements (SLAs) to its customers. Si...
Joel Sommers, Paul Barford, Albert G. Greenberg, W...
DATE
2004
IEEE
125views Hardware» more  DATE 2004»
9 years 3 months ago
Fast Comparisons of Circuit Implementations
Abstract-- Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing ca...
Shrirang K. Karandikar, Sachin S. Sapatnekar
ICCAD
2007
IEEE
91views Hardware» more  ICCAD 2007»
9 years 4 months ago
Sizing and placement of charge recycling transistors in MTCMOS circuits
Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram
DAC
2010
ACM
9 years 4 months ago
Eyecharts: constructive benchmarking of gate sizing heuristics
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla...
DAC
1997
ACM
9 years 4 months ago
Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the h...
James Kao, Anantha Chandrakasan, Dimitri Antoniadi...
ICCAD
1997
IEEE
118views Hardware» more  ICCAD 1997»
9 years 4 months ago
Global interconnect sizing and spacing with consideration of coupling capacitance
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of couplin...
Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang P...
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