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DATE
2004
IEEE
111views Hardware» more  DATE 2004»
9 years 12 months ago
State-Preserving vs. Non-State-Preserving Leakage Control in Caches
This paper compares the effectiveness of statepreserving and non-state-preserving techniques for leakage control in caches by comparing drowsy cache and gated-V
Yingmin Li, Dharmesh Parikh, Yan Zhang, Karthik Sa...
ASPDAC
2007
ACM
95views Hardware» more  ASPDAC 2007»
10 years 4 days ago
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits
Power gating has been widely used to reduce subthreshold leakage. However, its efficiency degrades very fast with technology scaling due to the gate leakage of circuits specific t...
Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun ...
ASPDAC
2005
ACM
193views Hardware» more  ASPDAC 2005»
10 years 1 months ago
VLSI on-chip power/ground network optimization considering decap leakage currents
- In today’s power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leak...
Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, ...
ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
10 years 2 months ago
Analysis and optimization of gate leakage current of power gating circuits
— Power gating is widely accepted as an efficient way to suppress subthreshold leakage current. Yet, it suffers from gate leakage current, which grows very fast with scaling dow...
Hyung-Ock Kim, Youngsoo Shin
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
10 years 2 months ago
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
Sanjeev K. Jain, Pankaj Agarwal
ISQED
2006
IEEE
109views Hardware» more  ISQED 2006»
10 years 2 months ago
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
DATE
2006
IEEE
142views Hardware» more  DATE 2006»
10 years 2 months ago
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
10 years 2 months ago
ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimiza...
Saraju P. Mohanty
ISLPED
2009
ACM
127views Hardware» more  ISLPED 2009»
10 years 2 months ago
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic
In this paper, we observe that minimum energy Emin of subthreshold logic dramatically increases when reaching 45 nm node. We demonstrate by circuit simulation and analytical model...
David Bol, Dina Kamel, Denis Flandre, Jean-Didier ...
VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
10 years 8 months ago
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
Saraju P. Mohanty, Elias Kougianos
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