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ET
2002
67views more  ET 2002»
9 years 3 months ago
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our te...
Emmanouil Kalligeros, Xrysovalantis Kavousianos, D...
TCAD
2008
114views more  TCAD 2008»
9 years 3 months ago
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
Zhanglei Wang, Krishnendu Chakrabarty
ITC
2000
IEEE
84views Hardware» more  ITC 2000»
9 years 7 months ago
Non-intrusive BIST for systems-on-a-chip
1 The term "functional BIST" describes a test method to control functional modules so that they generate a deterministic test set, which targets structural faults within ...
Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wund...
DAC
1994
ACM
9 years 8 months ago
Dynamic Search-Space Pruning Techniques in Path Sensitization
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
João P. Marques Silva, Karem A. Sakallah
ICCAD
1997
IEEE
147views Hardware» more  ICCAD 1997»
9 years 8 months ago
Built-in test generation for synchronous sequential circuits
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
Irith Pomeranz, Sudhakar M. Reddy
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
9 years 8 months ago
Partial scan delay fault testing of asynchronous circuits
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
Michael Kishinevsky, Alex Kondratyev, Luciano Lava...
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
9 years 8 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
9 years 8 months ago
Test pattern generation for width compression in BIST
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
Paulo F. Flores, Horácio C. Neto, K. Chakra...
DATE
2000
IEEE
130views Hardware» more  DATE 2000»
9 years 8 months ago
Optimal Hardware Pattern Generation for Functional BIST
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, H...
DAC
2003
ACM
9 years 9 months ago
Efficient compression and application of deterministic patterns in a logic BIST architecture
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
Peter Wohl, John A. Waicukauski, Sanjay Patel, Min...
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