ET
2002
13 years 4 months ago
2002
In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our te...
TCAD
2008
13 years 4 months ago
2008
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
ITC
2000
IEEE
13 years 8 months ago
2000
IEEE
1 The term "functional BIST" describes a test method to control functional modules so that they generate a deterministic test set, which targets structural faults within ...
DAC
1994
ACM
13 years 8 months ago
1994
ACM
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
ATS
1998
IEEE
13 years 8 months ago
1998
IEEE
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
ISCAS
1999
IEEE
13 years 8 months ago
1999
IEEE
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
DAC
2003
ACM
13 years 9 months ago
2003
ACM
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...