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DATE
2009
IEEE

A new design-for-test technique for SRAM core-cell stability faults

9 years 8 months ago
A new design-for-test technique for SRAM core-cell stability faults
—Core-cell stability represents the ability of the core-cell to keep the stored data. With the rapid development of semiconductor memories, their test is becoming a major concern in VDSM technologies. It provides information about the SRAM design reliability, and its effectiveness is therefore mandatory for safety applications. Existing core-cell stability Design-for-Test (DfT) techniques consist in controlling the voltage levels of bit lines to apply a weak write stress on the core-cell under test. If the core-cell is weak, the weak write stress induces the faulty swap of the core-cell. However, these solutions are costly in terms of area and test application time, and generally require modifications of critical parts of the SRAM (core-cell array and/or the structure generating the internal auto-timing). In this paper, we present a new DfT technique for stability fault detection. It consists in modulating the word line activation in order to perform an adjustable weak write stress o...
Alexandre Ney, Luigi Dilillo, Patrick Girard, Serg
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin
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