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DATE
2009
IEEE

Optimal sizing of configurable devices to reduce variability in integrated circuits

9 years 8 months ago
Optimal sizing of configurable devices to reduce variability in integrated circuits
This paper describes a systematic approach that facilitates yield improvement of integrated circuits at the post-manufacture stage. A new Configurable Analogue Transistor (CAT) structure is presented that allows the adjustment of devices after manufacture. The technique enables both performance and yield to be improved as part of the normal test process. The optimal sizing of the inserted CAT devices is crucial to ensure the greatest improvement in yield and this paper considers this challenge in detail. An analysis and description of the underlying theory of the sizing problem is given along with examples of incorrect sizing. Guidelines to achieve optimal CAT sizing are proposed, and results are provided to demonstrate the overall effectiveness of the CAT approach.
Peter Wilson, Reuben Wilcock
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Peter Wilson, Reuben Wilcock
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