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FPL
2008
Springer

Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA

9 years 11 months ago
Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. However, this approach results in inefficient memory utilization. Due to available on-chip memory and pin limitations of FPGAs, stateof-the-art designs on FPGAs cannot support large routing tables arising in backbone routers. Therefore, ternary content addressable memory (TCAM) is widely used. We propose a novel SRAM-based linear pipeline architecture, named DuPI. Using a single Virtex-4, DuPI can support a routing table of up to 228K prefixes, which is 3
Hoang Le, Weirong Jiang, Viktor K. Prasanna
Added 26 Oct 2010
Updated 26 Oct 2010
Type Conference
Year 2008
Where FPL
Authors Hoang Le, Weirong Jiang, Viktor K. Prasanna
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