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2002
IEEE

Test Pattern Generation for Signal Integrity Faults on Long Interconnects

10 years 3 months ago
Test Pattern Generation for Signal Integrity Faults on Long Interconnects
In this paper, we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and parasitic RLC elements of the interconnect. To enhance the performance of test generation process, model order reduction methodology is employed. This strategy significantly improves the simulation time with slight loss of accuracy.
Amir Attarha, Mehrdad Nourani
Added 16 Jul 2010
Updated 16 Jul 2010
Type Conference
Year 2002
Where VTS
Authors Amir Attarha, Mehrdad Nourani
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