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DAC
2011
ACM

TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC

8 years 7 months ago
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
In this work, we propose an efficient and accurate full-chip thermomechanical stress and reliability analysis tool and design optimization methodology to alleviate mechanical reliability issues in 3D ICs. First, we analyze detailed thermo-mechanical stress induced by TSVs in conjunction with various associated structures such as landing pad and dielectric liner. Then, we explore and validate the use of the linear superposition principle of stress tensors and demonstrate the accuracy of this method against detailed finite element analysis (FEA) simulations. Next, we apply this linear superposition method to full-chip stress simulation and a reliability metric named the von Mises yield criterion. Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs. Our experimental results demonstrate the effectiveness of our methodology. Categories and Subject Descriptors B.7.2 [Hardware, Integrated Circuit]: Design Aids General Terms Design...
Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Ky
Added 18 Dec 2011
Updated 18 Dec 2011
Type Journal
Year 2011
Where DAC
Authors Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim
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