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DATE
2004
IEEE
151views Hardware» more  DATE 2004»
13 years 9 months ago
Boosting: Min-Cut Placement with Improved Signal Delay
In this work we improve top-down min-cut placers in the context of timing closure. Using the concept of boosting factors, we adjust net weights according to net spans, so as to re...
Andrew B. Kahng, Igor L. Markov, Sherief Reda
DATE
2004
IEEE
210views Hardware» more  DATE 2004»
13 years 9 months ago
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. We present a...
Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru N...
DATE
2004
IEEE
142views Hardware» more  DATE 2004»
13 years 9 months ago
Eliminating False Positives in Crosstalk Noise Analysis
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. Noise analysis techniques can detect some of such noise faults, but accu...
Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Mal...
DATE
2004
IEEE
131views Hardware» more  DATE 2004»
13 years 9 months ago
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive differe...
Anuja Sehgal, Krishnendu Chakrabarty
DATE
2004
IEEE
121views Hardware» more  DATE 2004»
13 years 9 months ago
Experiences during the Experimental Validation of the Time-Triggered Architecture
During last years, the Time-Triggered Architecture (TTA) has been gaining acceptance as a generic architecture for highly dependable real-time systems. It is now being used to imp...
Sara Blanc, Joaquin Gracia, Pedro J. Gil
Hardware
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