9 search results - page 1 / 2 » A BIST Scheme for On-Chip ADC and DAC Testing |
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper, we present a BIST scheme for testing onchip AD and DA converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measurin...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— This paper presents a scheme for testing DACs’ static non-linearity errors by using a two-step flash ADC with deterministic dynamic element matching (DDEM). In this work, the...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design...
ITC
1993
IEEE
13 years 8 months ago
1993
IEEE
Built-In-Self-Test BIST for VLSI systems is desirable in order to reduce the cost per chip of production-time testing by the manufacturer. In addition, it can provide the means ...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
