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» A BIST Scheme for On-Chip ADC and DAC Testing
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DATE
2000
IEEE
110views Hardware» more  DATE 2000»
14 years 3 months ago
A BIST Scheme for On-Chip ADC and DAC Testing
In this paper, we present a BIST scheme for testing onchip AD and DA converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measurin...
Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng
ISCAS
2005
IEEE
153views Hardware» more  ISCAS 2005»
14 years 4 months ago
A two-step DDEM ADC for accurate and cost-effective DAC testing
— This paper presents a scheme for testing DACs’ static non-linearity errors by using a two-step flash ADC with deterministic dynamic element matching (DDEM). In this work, the...
Hanqing Xing, Degang Chen, Randall L. Geiger
DATE
2002
IEEE
89views Hardware» more  DATE 2002»
14 years 3 months ago
A Hierarchical Test Scheme for System-On-Chip Designs
System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design...
Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pi...
ITC
1993
IEEE
104views Hardware» more  ITC 1993»
14 years 2 months ago
A BIST Scheme for an SNR Test of a Sigma-Delta ADC
Built-In-Self-Test BIST for VLSI systems is desirable in order to reduce the cost per chip of production-time testing by the manufacturer. In addition, it can provide the means ...
M. F. Toner, Gordon W. Roberts