14 search results - page 1 / 3 » A BIST Structure to Test Delay Faults in a Scan Environment |
ATS
1998
IEEE
13 years 9 months ago
1998
IEEE
VTS
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
IOLTS
2006
IEEE
13 years 10 months ago
2006
IEEE
— Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. Howeve...
IOLTS
2000
IEEE
13 years 9 months ago
2000
IEEE
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
ET
2006
13 years 4 months ago
2006
We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIS...