14 search results - page 3 / 3 » A BIST Structure to Test Delay Faults in a Scan Environment |
VTS
2000
IEEE
13 years 9 months ago
2000
IEEE
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
ITC
1997
IEEE
13 years 9 months ago
1997
IEEE
Tri-state buses and pass transistor logic are used in many complex applications to achieve high performance and small area. Such circuits often contain logic requiring one-hot sig...
ATS
2010
IEEE
13 years 1 months ago
2010
IEEE
Systems with many integrated circuits (ICs), often of the same type, are increasingly common to meet the constant performance demand. However, systems in recent semiconductor techn...
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...