13 search results - page 2 / 3 » A Bit-Node Centric Architecture for Low-Density Parity-Check... |
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Low-Density Parity Check codes are a form of Error Correcting Codes used in various wireless communication applications and in disk drives. While LDPC codes are desirable due to t...
ICASSP
2011
IEEE
12 years 8 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— Low-Density Parity-Check Convolutional Codes (LDPC-CCs) are an attractive alternative to their block-oriented counterparts, LDPC-BCs. In this paper, we introduce these codes an...
SIPS
2007
IEEE
13 years 11 months ago
2007
IEEE
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
ASAP
2006
IEEE
13 years 6 months ago
2006
IEEE
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...