15 search results - page 1 / 3 » A Circuit Level Fault Model for Resistive Opens and Bridges |
VTS
2003
IEEE
13 years 10 months ago
2003
IEEE
Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are...
ITC
1999
IEEE
13 years 9 months ago
1999
IEEE
Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are ed to voltage behavior for use in voltage-level fault simulation and te...
VTS
1996
IEEE
13 years 9 months ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
DATE
2008
IEEE
13 years 12 months ago
2008
IEEE
We report the successful application of a resistive bridging fault (RBF) simulator to industrial benchmark circuits. Despite the slowdown due to the consideration of the sophistic...
ET
2007
13 years 5 months ago
2007
In this paper, we present an exhaustive study on the influence of resistive-open defects in pre-charge circuits of SRAM memories. In SRAM memories, the pre-charge circuits operate...