4 search results - page 1 / 1 » A High Performance Hybrid Wave-Pipelined Multiplier |
ISVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
The clock period in conventional pipeline scheme is proportional to the maximum delay while in hybrid wave-pipelining it is proportional to the maximum delay difference. An 8×8-b...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
In this paper, we present a novel hybrid multiplier architecture that has the regularity of linear array multipliers and the performance of tree multipliers and is highly scalable...
CODES
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...