32 search results - page 1 / 7 » A New Full Adder Cell for Low-Power Applications |
GLVLSI
1998
IEEE
13 years 9 months ago
1998
IEEE
GLVLSI
1999
IEEE
13 years 9 months ago
1999
IEEE
A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this paper. The power consumption and general characteristics of the SERF adder...
JCP
2008
13 years 4 months ago
2008
In this paper a new low power and high performance adder cell using a new design style called "Bridge" is proposed. The bridge design style enjoys a high degree of regula...
ISLPED
1999
ACM
13 years 9 months ago
1999
ACM
This paper describes a new mixed-swing topology for dual-rail domino logic that results in a simultaneous energy and delay reduction. HSPICE simulation results for a 1-bit full ad...
CSREAESA
2004
13 years 6 months ago
2004
In this paper, we survey various designs of low-power full-adder cells from conventional CMOS to really inventive XOR-based designs. We further describe simulation experiments tha...