32 search results - page 2 / 7 » A New High Density and Very Low Cost Reprogrammable FPGA Arc... |
NOCS
2007
IEEE
14 years 1 days ago
2007
IEEE
We present a novel network-on-chip-based architecture for future programmable chips (FPGAs). A key challenge for FPGA design is supporting numerous highly variable design instance...
FPL
2005
Springer
13 years 11 months ago
2005
Springer
This paper describes novel data-path architecture for FPGA-based multimedia processors. The proposed circuit can adapt itself at run-time to different operations and data wordleng...
DATE
2009
IEEE
14 years 16 days ago
2009
IEEE
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available high definition frame sizes and hi...
FPL
2009
Springer
13 years 10 months ago
2009
Springer
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
DAC
2009
ACM
13 years 9 months ago
2009
ACM
Structured ASICs have recently emerged as an exciting alternative to ASIC or FPGA design style as they provide a new trade-off between the high performance of ASIC design and low ...