60 search results - page 2 / 12 » A Test Point Insertion Algorithm for Mixed-Signal Circuits |
ITC
2002
IEEE
13 years 10 months ago
2002
IEEE
Efficient production testing is frequently hampered because current digital circuits require test sets which are too large. These test sets can be reduced significantly by means...
VTS
1996
IEEE
13 years 10 months ago
1996
IEEE
This paper presents an innovative method for inserting test points in the circuit-under-test to obtain complete fault coverage for a specified set of test patterns. Rather than us...
VLSID
2002
IEEE
14 years 6 months ago
2002
IEEE
ICCAD
1995
IEEE
13 years 9 months ago
1995
IEEE
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
DAC
1996
ACM
13 years 10 months ago
1996
ACM
We propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses th...